Sanjay Churiwala is Senior Director of Engineering for Xilinx India Technology Services. He has extensive experience in the field of EDA and semiconductors R&D, as well as customer-interaction. He specializes in Clock Domain Crossings and Synchronization, STA, Power, Synthesis, Simulation, Rule based static checkers, Cell Characterization and Modeling.

Emphasizes concepts, particularly which device characteristics are important, and how they influence a user's design realization

Uses a systematic approach to achieving design target goals, such as Power and Timing

Explores the various ways to enter design information and read back/analyze a design realization

Demonstrates use of some of the most widely used IP Cores

Explains debugging of designs on Xilinx devices and using Xilinx Tools

Includes supplementary material: [...]

State of the Art Programmable Logic.- Vivado Design Tools.- IP Flows.- Gigabit Transceivers.- Memory Controllers.- Processor Options.- Vivado IP Integrator.- SysGen for DSP.- Synthesis.- C Based Design.- Simulation.- Clocking.- Stacked Silicon Interconnect.- Timing Closure.- Power Analysis and Optimization.- System Monitor.- Hardware Debug.- Emulation Using FPGAs.- Partial Reconfiguration & Hierarchical Design.